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author | Ben Bridle <ben@derelict.engineering> | 2025-02-05 12:58:02 +1300 |
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committer | Ben Bridle <ben@derelict.engineering> | 2025-02-05 13:03:36 +1300 |
commit | 80da2af821385b2fc89091e9ac37a047349da4bd (patch) | |
tree | 2ba50368301e041f8d1b99145ab0a1fe28f91571 /src/errors/merge_error.rs | |
parent | 8d11be64f6c1747e7c4049105a6dd4ea9ab0d27f (diff) | |
download | assembler-80da2af821385b2fc89091e9ac37a047349da4bd.zip |
Implement source unit compilation, symbol resolution, error reporting
This library can now carry out all stages of assembly from collecting
source fragments to resolving symbols to pruning unused libraries to
generating a single compiled source file.
Pretty-printing of state has also been implemented in this library.
The source tree hierarchy, symbol resolution errors, and file read
errors can all be printed in a tidy format.
Diffstat (limited to 'src/errors/merge_error.rs')
-rw-r--r-- | src/errors/merge_error.rs | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/errors/merge_error.rs b/src/errors/merge_error.rs new file mode 100644 index 0000000..a694b71 --- /dev/null +++ b/src/errors/merge_error.rs @@ -0,0 +1,41 @@ +use crate::*; + +use ansi::*; +use log::error; + + +pub struct MergeError<'a> { + pub resolver: &'a Resolver, + /// A list of source units involved in a cycle. + pub cyclic_unit_ids: Vec<usize>, +} + +impl MergeError<'_> { + pub fn report(&self) { + error!("A cyclic dependency was found between the following libraries:"); + for id in &self.cyclic_unit_ids { + if let Some(unit) = self.resolver.source_units.get(*id) { + let path = &unit.source_unit.path(); + match unit.source_unit.name() { + Some(name) => + eprintln!("{name}{NORMAL}{DIM} ({path}){NORMAL}"), + None => + eprintln!("{path}"), + }; + // Print each parent involved in the dependency cycle. + for parent_id in &unit.parent_ids { + if !self.cyclic_unit_ids.contains(parent_id) { continue; } + if let Some(parent_unit) = self.resolver.source_units.get(*parent_id) { + let parent_path = &parent_unit.source_unit.path(); + match parent_unit.source_unit.name() { + Some(parent_name) => + eprintln!(" => {parent_name} {DIM}({parent_path}){NORMAL}"), + None => + eprintln!(" => {parent_path}"), + }; + } + } + } + } + } +} |