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authorBen Bridle <bridle.benjamin@gmail.com>2024-10-07 19:45:57 +1300
committerBen Bridle <bridle.benjamin@gmail.com>2024-10-07 19:45:57 +1300
commitf71aa759098369428e6610c8c35f51ac50a44d73 (patch)
tree43ec280d2ccd92077c7fd989d937c096e8a377b3 /src/processor.rs
parentf4f129a75208ccf5d6a19b1cb81c56d4d95fd61f (diff)
downloadbedrock-core-f71aa759098369428e6610c8c35f51ac50a44d73.zip
Record total elapsed processor cycles
Diffstat (limited to 'src/processor.rs')
-rw-r--r--src/processor.rs5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/processor.rs b/src/processor.rs
index 6c5362a..bc16f01 100644
--- a/src/processor.rs
+++ b/src/processor.rs
@@ -101,7 +101,10 @@ impl <
};
}
- for _ in 0..cycles {
+ let end = self.cyc + cycles;
+ while self.cyc < end {
+ self.cyc += 1;
+
match self.mem.read_u8_next() {
/* HLT */ 0x00 => { return Some(Signal::Halt); }
/* JMP */ 0x01 => { WPOPD!(a); self.mem.pc=a; }