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author | Ben Bridle <ben@derelict.engineering> | 2025-04-12 10:19:26 +1200 |
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committer | Ben Bridle <ben@derelict.engineering> | 2025-04-12 10:19:26 +1200 |
commit | dddb76c4ad504022fa4f4c4f6965c08da22c387e (patch) | |
tree | 735d80e0a18566bfa649afe5c9e1e6c076ae1c33 /src | |
parent | c724c9157dbc4721fa8ed93033cd9699c9652277 (diff) | |
download | torque-asm-dddb76c4ad504022fa4f4c4f6965c08da22c387e.zip |
Fix width checks for negative integers
The width of a negative integer was previously being counted in the
same way as for a positive integer, by inverting the bits to make it a
positive integer and then finding the placement of the highest-order 1
bit.
The actual width of a negative integer will always be one greater than
this value however, because the highest-order 1 bit of an inverted
negative integer will always have directly above it a significant 0 bit
used as the sign bit.
Diffstat (limited to 'src')
-rw-r--r-- | src/stages/bytecode.rs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/stages/bytecode.rs b/src/stages/bytecode.rs index 3618b26..e4464a1 100644 --- a/src/stages/bytecode.rs +++ b/src/stages/bytecode.rs @@ -163,7 +163,7 @@ impl BytecodeParser { } }; let value_width = match field_value.cmp(&0) { - std::cmp::Ordering::Less => (-field_value).ilog2() + 1, + std::cmp::Ordering::Less => (-field_value).ilog2() + 2, std::cmp::Ordering::Equal => 0, std::cmp::Ordering::Greater => field_value.ilog2() + 1, }; |