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authorBen Bridle <ben@derelict.engineering>2025-03-25 12:00:15 +1300
committerBen Bridle <ben@derelict.engineering>2025-03-25 12:00:15 +1300
commitc23c47325a7818c4df4097878f101cd80e2fe361 (patch)
treef7d591c90428d43064be10de660021c2cd6dc863 /src/components/device_bus.rs
parent179bd6a13d91f0a1137ee8ed6aebb7e226e99b5d (diff)
downloadbedrock-core-c23c47325a7818c4df4097878f101cd80e2fe361.zip
Partially restructure the library
This also changes bit-shifting semantics, shifting left and then right instead of the other way around.
Diffstat (limited to 'src/components/device_bus.rs')
-rw-r--r--src/components/device_bus.rs22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/components/device_bus.rs b/src/components/device_bus.rs
new file mode 100644
index 0000000..9854ee9
--- /dev/null
+++ b/src/components/device_bus.rs
@@ -0,0 +1,22 @@
+use crate::*;
+
+
+pub trait DeviceBus {
+ fn read(&mut self, port: u8) -> u8;
+ fn write(&mut self, port: u8, value: u8) -> Option<Signal>;
+ fn wake(&mut self) -> bool;
+}
+
+
+pub trait Device {
+ fn read(&mut self, port: u8) -> u8;
+ fn write(&mut self, port: u8, value: u8) -> Option<Signal>;
+ fn wake(&mut self) -> bool;
+}
+
+impl Device for () {
+ fn read(&mut self, _: u8) -> u8 { 0 }
+ fn write(&mut self, _: u8, _: u8) -> Option<Signal> { None }
+ fn wake(&mut self) -> bool { false }
+}
+